
23
FN6808.3
October 1, 2009
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the
data transfer. By default, all data is presented on the serial
data input/output (SDIO) pin in three-wire mode. The state of
the SDIO pin is set automatically in the communication
protocol (described in the following). A dedicated serial data
output pin (SDO) can be activated by setting 0x00[7] high to
allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5512HP functioning as a slave.
FIGURE 35. SPI WRITE
tS
tHI
tCLK
tLO
R/W
W1
W0
A12 A11 A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
tH
tDHW
tDSW
SPI WRITE
CSB
SCLK
SDIO
FIGURE 36. SPI READ
(3 WIRE MODE)
(4 WIRE MODE)
R/W
W1
W0
A12 A11 A10
A9
A2
A1
D7
D6
D3
D2
D1
D7
D3
D2
D1 D0
A0
WRITING A READ COMMAND
READING DATA
D0
tH
tDHR
tDVR
SPI READ
tHI
tCLK
tLO
tDHW
tDSW
tS
CSB
SCLK
SDIO
SDO
FIGURE 37. 2-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
CSB STALLING
FIGURE 38. N-BYTE TRANSFER
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
LAST LEGAL
CSB STALLING
KAD5512HP